1. Field of the Invention
This invention is related to the field of processors and, more particularly, to handling caches and cache coherency in power management modes in processors.
2. Description of the Related Art
As the power consumption of processors has increased, implementation of power management modes in processors has become increasing important. In many systems, the power supply is at least sometimes a battery or other stored-charge supply. Maximizing battery life in such systems is often a key selling feature. Additionally, even in systems that have effectively limitless power (e.g. systems plugged into a wall outlet), the challenges of cooling the processors and other circuits in the system may be reduced if the processors can be placed in low power modes when full processing power is not needed.
A variety of power management schemes are in use. Typically, the processor may be operated in one of a set of power states. The highest power state is the state in which the processor executes at its maximum operating frequency, typically supplied by the highest supply voltage used in any of the power states. In some cases, other power states are defined in which the processor operates at lower operating frequencies and/or lower supply voltages (or the lower frequencies/voltages may be used without actually causing a power state transition). Additionally, one or more lower power states are typically defined in which the processor clocks are inhibited (also referred to as disabled the clocks or “turning off” the clocks). Since the processor clocks are not toggling, logic in the processor does not change state and the power consumed by the processor may be largely reduced. In some low power states, the processor is still supplied with supply voltage to permit the state of the processor, including any caches, to be retained even though the clocks are disabled. In other low power states, the supply voltage may be deactivated as well and the processor state is lost. Typically, the processor must be reset from a low power state in which the processor's supply voltage was deactivated.
A challenge in processors that implement low power states in which the supply voltage is maintained, and thus the caches retain their state, is the maintenance of coherency in the caches with respect to any memory transactions that may be generated by other devices/processors while the processor is in the low power state. In some cases, systems “wake up” the processor to a higher power state to perform a snoop (and then return the processor to the low power state). Power is consumed in waking up the processor, often for a snoop that does not hit in the cache. In other cases, the processor is designed to continue clocking the cache and a portion of the processor that interfaces to the cache during the low power states. The cache and related circuitry is thus in a different clock domain than the rest of the processor, which complicates the overall processor design.